LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY WcDecoder_tb IS
END WcDecoder_tb;

ARCHITECTURE archWcDecoder_tb OF WcDecoder_tb IS
	COMPONENT WcDecoder IS
		PORT (
			--2 switch input
			UCP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
			--player
			P : IN STD_LOGIC;
			--place to shore the result
			WC : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
	END COMPONENT;

	SIGNAL UCP, WC : STD_LOGIC_VECTOR(1 DOWNTO 0);
	SIGNAL P : STD_LOGIC;

BEGIN
	UUT : WcDecoder PORT MAP(UCP, P, WC);
	sim_proc : PROCESS
	BEGIN
		p <= '0';
		UCP <= "00";
		WAIT FOR 50 ns;

		UCP <= "01";
		WAIT FOR 50 ns;

		UCP <= "10";
		WAIT FOR 50 ns;

		UCP <= "11";
		WAIT FOR 50 ns;

		p <= '1';
		UCP <= "00";
		WAIT FOR 50 ns;

		UCP <= "01";
		WAIT FOR 50 ns;

		UCP <= "10";
		WAIT FOR 50 ns;

		UCP <= "11";
		WAIT FOR 50 ns;
		WAIT;
	END PROCESS;
END archWcDecoder_tb;